Automatic Generation of Parallel Code for Multi/Many-Core Systems with High Reliability and Performance by utilizing Model Diagrams and C Source Code
eMBP® (Model Based Parallelizer) uses models designed with the MathWorks® Simulink® design tool to automatically generate parallel code for multi- and many-core systems with high reliability and performance.
Model-based development (MBD) enhances design quality and final system reliability, and is increasingly being adopted in applications with stringent safety demands, including in-vehicle ECUs and in the aerospace industry. Use of intelligent functions is growing in these applications, and with this comes a need for multi- and many-core technologies that offer excellent performance and power efficiency. Unfortunately, existing MBD and parallelization tools are not well suited to generating code that is optimized for multi- and many-core systems. This makes it difficult to identify where parallelism can be used and to achieve the optimal allocation of parallel programs to cores and at the same time ensure safety and real-time capability.
Using Simulink models as its input, eMBP automatically generates parallel code with higher reliability and execution efficiency, which reflects the intention of the design. While parallelization of control algorithms is difficult to achieve through analysis of C source code alone, eMBP makes it easy to achieve in a way that accurately reflects the designer’s intentions. Because eMBP can use models with a higher level of abstraction than the C source code used by existing parallelization tools, it helps reduce both development time and cost.
eMBP was developed by eSOL, and sales and product support are provided by eSOL TRINITY Co., Ltd. Contact eSOL TRINITY for any inquiries related to product deployment.
- Generates parallel code from C source code and MathWorks® Simulink® control model
- Achieves parallelism in the control algorithm in accordance with the designer's intensions by analyzing the Simulink block diagram to identify data flows correctly from the diagram signal lines
- Integrates blocks that are able to be executed in parallel by critical path analysis and allocates to the appropriate core based on a minimum cut strategy
- Uses the XML-based Software-Hardware Interface for Multi-Many Core (SHIM) format of The Multicore Association (standardized as IEEE Std 2804-2019) to estimate performance
- The eMBP Renesas RH850 PILS Package is available to use processor-in-the-loop simulation (PILS) of Renesas Electronics RH850 multi-core processor for performance estimation.
Block structure extraction
The block structure browser identifies opportunities for parallel execution at the block level from the Simulink model.
Once extracted, the tool estimates execution performance based on the architecture and performance data of the multi- or many-core processor to be implemented. These performance estimates use the XML-based Software-Hardware Interface for Multi-Many Core (SHIM) format of The Multicore Association. Using the SHIM format allows integrating platform hardware information, to further refine the best technique to parallelize the algorithms.
Block to core assignment
Core mapping groups together blocks that can be executed in parallel and assigns them to cores.
Parallel code generation
Once properly configured, the tool automatically generates parallelized C source code.
An intuitive display tool allows looking at the relationships between the blocks that have been grouped for each core.
eMBP Adaptor for Renesas PILS
This platform-specific addition enables eMBP to work with a Processor-In-The-Loop Simulation (PILS) environment for RH850 multi-core microcontrollers made by Renesas Electronics. It includes a block structure extraction function, and a core mapping function based on accurate performance estimation using PILS.
Details of "Embedded Target for RH850 Multicore" of Renesas Electronics